The Design, Part 2: The ALU.

I have nearly completed the initial design of the ALU.

There are still some bits missing, and I havent simulated the whole ALU yet, only partly att block-level

It will support the following primitive functions:

  • AND
  • OR
  • NOR
  • XOR
  • ADD
  • SUB
  • SLT

Here is a screenshot of the ALU

Schematic Editor ( Circuit _ 1-BIT_ALU - Page _ MAINPAGE ) [Project _ ECL] Page _ 1

And the more readable pdf-file Main ALU

There is also a register section, 3 registers (at the moment) one bit per slice.

Schematic Editor ( Circuit _ 1-BIT_ALU - Page _ REG ) [Project _ ECL] Page _ 1

The pdf: Registers

There is three register A, B and Result.
the registers consist of one D Flip-Flop, per gate together with demultiplexers for selecting the function

The following operations is supported, it probably will be changed in the future:

  • CPYMA (copy from Data-bus to A)
  • CPYMB
  • CPYRM ( Copy Result to Data-bus)
  • CPYRA (Copy Result to A)
  • CPYRB

When you look at the schematics, it might be a Little bit strange, but using ECL has an advantage compared to other families, The complementary output is easily accessible, which means that I can use that to reduce the number of gates needed.

For example, if I need an 2-input AND-Gate, you will use two inverters on the input of a NOR-Gate, thus, using the inverted output off the previous gate, instead of the normal output, I can omitt the inverters, saving two gates (Three transistors per gate).

This is basically what will go on each ALU-Slice Circuit board, together with the Biasing Circuit (I am also playing with the Idea of having a common Bias Circuit for the whole computer).

Apart from the above, there will also be a separate PCB for Look-Ahead Carry, as well as status register and Zero detecting Circuit.

One thought on “The Design, Part 2: The ALU.

  1. admin Post author

    There is a small error on the schematic, the Connections between AND and /AND and the result MUX should be swapped.

    Reply

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